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*Kicks self*	by AndyA	2008-10-01 11:00:00
I've spent the best part of a day trying to tweak the xilinx tools so that my design met the timing requirements. No matter what I did a couple of signals were working out 0.25ns too slow. I finally bit the bullet and added an extra clock cycle delay along the critical paths and it now all works easily. Just as the compiler was telling me that everything now met the timing requirements I noticed that the target part it was using was incorrectly. I've actually got a faster speed grade part than the tools think, if that setting was correct it would probably have worked fine a day ago. Oh well, at least I've got more safety margin now.
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Kicks AndyA	by ag__wyvern	2008-10-01 11:02:50

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