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Oh, so I was thinking last night...	by Llyr	2003-07-10 07:50:34
I would guess	by Egaeus	2003-07-10 08:01:48
The simplifying assumptions are what make it fun.	by Llyr	2003-07-10 08:03:32
mumbles something about silly physicists	by Egaeus	2003-07-10 08:07:43
Well I know where they went wrong.	by taIon	2003-07-10 09:04:14
I love VHDL!	by Egaeus	2003-07-10 09:09:18
No book recomendations	by taIon	2003-07-10 09:38:05
I've never seen one on either of them other than quick referance guides. But having done about 30,000 lines of VHDL and 8,000 of verilog I know which I prefer. I would like to have done more but there is the minor issue of having to design the boards to put the code on. Verilog normally comes out between 30 and 50% less code to do the same thing. e.g. counters automatically wrap around rather then being dependant on the compiler. vectors and integers are interchangable rather than having to convert or use the correct library. It's just faster and easier to use. VHDL has one plus point. For a larger project with multiple people working on it and with a large amount of design simulation and verification then VHDL is better. It's stricter rules just make it safer for that sort of project. That said I've worked on million gate designs in verilog, as long as the interface between blocks is well documented then there aren't any problems.
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